1. Field of the Invention
The present invention relates to the structure of an insulated gate semiconductor device formed using a crystalline semiconductor substrate, for example, a monocrystal silicon substrate or an SOI substrate (SIMOX or the like), and more particularly to the structure of an insulated gate field effect transistor (hereinafter referred to simply as “IG-FET”) and a method of manufacturing the same. The present invention relates to a technique of which advantages are especially exhibited in the case of manufacturing a fine device whose channel length is 1 μm or less (representatively, 0.01 to 0.35 μm).
Therefore, the present invention is applicable to a semiconductor integrated circuit such as an IC, a VLSI or a ULSI, which is structured with integrated IG-FETs.
2. Description of the Related Art
In recent years, integrated circuits such as the VLSI are kept on becoming more fine, and the machining dimensions in the order of a deep sub-micron are required, for example, the width of a wiring is 0.18 μm or less, further 0.1 μm or less.
Up to now, the fining of a semiconductor device is progressed in accordance with the scaling rule, and there has been generally known that the fining leads to an improvement in the characteristic of the integrated circuit. However, the fine machining in the order of the sub-micron suffers from a problem that it does not simply accord to the scaling rule.
The representative problem of this type as known is a phenomenon such as a short channel effect. The short channel effect is the phenomenon caused by the reason that as the line width of a gate electrode is shortened, that is, a channel formation region is shortened the charges in the channel formation region becomes to be largely influenced by not only a gate voltage but also the charges in a depletion layer of a source/drain region, an electric field and a potential distribution.
This state is simplified and shown in FIG. 3. Reference numeral 301 denotes a source region, reference numeral 302 denotes a drain region, reference numeral 303 denotes a channel region, and reference numeral 304 denotes a gate electrode. Also, a dotted line indicated by reference numeral 305 represents a depletion layer which is formed when a drain voltage Vd is small.
Normally, a current that flows in the channel region 303 is controlled by only a gate voltage Vg. In this case, as indicated by reference numeral 305, since the depletion layer which is in the vicinity of the channel region 303 is substantially in parallel with the channel, a uniform electric field is formed.
However, as the drain voltage Vd becomes high, the depletion layer which is in the vicinity of the drain region 302 is expanded toward the channel region 303 and the source region 301, with the result that as indicated by a solid line 306, the charge and the electric field in the drain depletion layer become to influence the depletion layer which is in the vicinity of the source region 301 and the channel region 303. In other words, an on-state current is changed according to a complicated electric field distribution, thereby making it difficult to control the current which flows in the channel region 303 by only the gate voltage Vg.
Here, an energy state in the periphery of the channel formation region when the short channel effect occurs will be described with reference to FIG. 4. In FIG. 4, state graphs indicated by solid lines represent energy bands of the source region 401, the channel formation region 402 and the drain region 403, respectively, when the drain voltage is 0 V.
In this state, when the drain voltage Vd which is sufficiently large is applied, the energy bands are changed into the states indicated by dotted lines in FIG. 4. In other words, the depletion charges and the electric field in the drain region 103 which are formed by the drain voltage Vd influence the charges in the depletion layers of the source and channel regions 401 and 402 so that an energy (potential) state is continuously changed from the source region 401 to the drain region 403.
The deterioration of a threshold value voltage (Vth) and a punch-through phenomenon have been well known as an influence of such a short channel effect on the semiconductor device, for example, the IG-FET. Also, there has been known that a sub-threshold characteristic is deteriorated when an influence of the gate voltage on the drain current by the punch-through phenomenon is lowered.
First, the deterioration of the threshold value voltage is a phenomenon that occurs in an n-channel FET and a p-channel FET, similarly. Also, the degree of the deterioration depends on not only the drain voltage but also a variety of parameters such as the concentration of impurities in a substrate, the depth of source/drain diffusion layer, the thickness of a gate oxide film, a substrate bias and so on.
The deterioration of the threshold value voltage is desirable from a viewpoint of lowering a power consumption, however, there generally arises such a disadvantage that a frequency characteristic is not increased because the drive voltage of the integrate circuit becomes small.
Under that circumstance, up to now, as means for controlling the threshold value voltage, it is general to uniformly add the impurity elements that give one conduction to the entire channel formation region, to control the threshold value voltage with the amount of addition of the impurity elements. However, even with this method, the short channel effect per se cannot be prevented, and the punch-through phenomenon is caused to occur. Also, since the added impurities allow carriers to be scattered, the mobility of carriers is caused to be lowered.
Also, the deterioration of the sub-threshold characteristic which is accompanied by the punch-through phenomenon means that the sub-threshold coefficient (S value) is increased, that is, the switching characteristic of an FET is deteriorated. An influence of the short channel effect on the sub-threshold characteristic is shown in FIG. 5.
FIG. 5 is a graph taking the gate voltage Vg in a horizontal axis and the logarithm of the drain current Id in a vertical axis. The inverse number of a slope (sub-threshold-characteristic) in the region 501 is an S value. In FIG. 5, the changes of characteristics when gradually shortening the channel length are compared, and the channel length is shortened toward a direction indicated by an arrow.
As a result, there can be confirmed that the slope of the-characteristic is decreased, that is, the S value is tended to be increased with the channel length being shortened. This means that the switching characteristic of the FET is deteriorated with the channel length being shortened.
The above-description is made to the short channel effect in the case of extremely shortening the length of the channel formation region of the semiconductor device. In the case of extremely narrowing the width of the channel formation region, the phenomenon such as the narrow channel effect also occurs.
What is shown in FIG. 6 is a cross-sectional view showing a normal IG-FET being cut on a plane perpendicular to the channel direction (a direction connecting the source and the drain). Reference numeral 601 denotes a monocrystal silicon substrate, and reference numeral 602 denotes a field oxide film formed through the selectively oxidizing method. The respective semiconductor devices used in the VLSI are separated by the field oxide film 602, respectively.
Also, reference numeral 603 denotes a gate electrode to which a voltage is applied to form a channel region 604. Impurity region 605 is disposed below the field oxide film 602 and functions as a channel stopper.
The narrow channel effect is caused in such a manner that a bird beak portion is which is an intrusion of the field oxide film 602 and the impurity region 605 into the channel region 604 largely influences the channel region 604 as the channel width W is narrowed. In particular, there may be cited an increase in the threshold value voltage and a dependency of the effective channel width on a supply voltage.
In the existing semiconductor industry, a semiconductor integrated circuit which has been integrated up to the limit has been demanded, and it is important to which degree the fining of the respective semiconductor devices can be pursued. However, even if a technique to form a fine pattern in the order of the deep sub-micron is developed, the problem of the above-mentioned short channel effect leads to a fatal obstacle that obstructs the fining of the device.